1. Field of the Invention
The present invention relates to a flip-flop with a scan path function that can shorten a setup time to achieve a high-speed operation, and particularly to a flip-flop with a scan path function employed for higher speed microprocessors.
2. Description of the Prior Art
As LSIs are more integrated year after year, conventional techniques hardly test these LSIs. To cope with this, some measures are needed. As one of the measures, a flip-flop (F/F) with a scan path has been proposed.
FIG. 1 shows a conventional F/F circuit with a scan path. In the figure, reference marks .phi. and .phi. denote a clock pulse signal and an inverted clock pulse signal respectively, D a data input terminal, S a test data input terminal, E an enable signal terminal and T a test enable signal terminal.
FIGS. 2(A) and 2(B) show signals of a clocked inverter which is activated with E=1, and a corresponding circuit diagram. FIG. 2(C) is a truth table of the signals. To activate the clocked inverter with E=0, the signals E and E of FIG. 2(B) may be replaced with each other, and 0s and 1s for the E of FIG. 2(C) may be replaced with each other. In the table of FIG. 2(C), "*" denotes a high impedance state.
The contents of a conventional F/F which is arranged in a circuit are usually influenced by logic circuits on the downstream side of the F/F and, therefore, hardly observed as they are. In addition, an output value of the F/F fed back to a combinational circuit indicates a previous value, so that the F/F has poor controllability and requires a large number of input vectors.
On the other hand, the F/F with a scan path is easy to monitor, and its output may optionally be set irrespective of the previous state, thereby enabling a sequential circuit to be tested as a combinational circuit.
The F/F of FIG. 1 is of a master-slave type whose data input portion controls a scan path test.
An operation of an edge trigger master-slave flip-flop (F/F) will be explained with reference to a circuit diagram of FIG. 3(A) and a timing chart of FIG. 3(B).
Unlike the F/F of FIG. 1, the F/F of FIG. 3(A) has complimentary outputs. The F/F of FIG. 3(A) comprises a master circuit MF/F for receiving data, and a slave circuit SF/F for holding the data. In synchronism of edges of a clock signal, input data D of the F/F is established, and an output data of the F/F changes. When the master F/F receives data, the slave F/F holds and outputs data of a previous cycle. When a data incoming portion 15 of the master F/F closes, a data incoming portion 17 of the slave F/F opens to receive data from the master F/F and update output data.
A test enabled state of the F/F with a scan path of FIG. 1 will be explained.
Input data passes through two clocked inverters comprising a multiplexer for scan input and a multiplexer for data feedback. The input data passes three stages of clocked inverters until it enters the master F/F. A setup time of the F/F, therefore, involves a delay time produced by the three stages of clocked inverters.
The delay of the three stages of clocked inverters prevents the F/F from improving its operation speed. There are many gates the input data has to pass through until the data enters the master F/F, and these gates delay the setup time which must be very short for speeding up data input, thereby preventing an improvement of operation frequency. In addition, the multiplexers interposed before the F/F increase a cell area, thereby enlarging the size of the F/F.
To solve these problems, the present invention provides a flip-flop with a scan path, which realizes a short input setup time, a high-speed operation, and compactness.